The Witcher 3 and Stray can now run on a 64-core RISC-V processor

In the world of modern computing architectures, the vast majority of people will only ever interact with Arm or x64_64 these days. There are other architectures out there as well, but none that are really as pervasive in day-to-day life. However, one architecture known as RISC-V has been growing over the years. It’s an open-standard ISA that anyone can modify and implement, making it a particularly interesting one that could challenge Arm in the long run. Now, the developers of Box64 have managed to get The Witcher 3 running on a RISC-V CPU with an AMD Radeon RX550.

Development is advancing fast

It uses Box64, Wine, and DXVK

The developers of Box64 have been hard at work over the last year attempting to get Box64 working fully on RISC-V. Box64, according to the lead developer, ptitSeb, is both a translation layer and an emulator. He told me the following:

There is the translation layer for the system library, convertings call from x86_64 ABI to the native one. But there is also the emulation part, with all the x86_64 binary (and non-wrapped library) because translated to native code on the fly. The emulation of the x86_64 code has to be as close to real thing as possible (becasue some encryption / obfuscation tools rely on exact opcode behaviour).

What is sure, it that there is no “full machine” emulation going on. No hardware emulation, no spicific timing, nothing like that, it’s limited to CPU emulation because it’s in “use-space” emulation and it provide a virtual x86_64 linux environement to the program.

That same concept applies to the RISC-V execution here, too. The Witcher 3 is running via a combination of translation and emulation, which allows it to run at an acceptable framerate on a 64-core RISC-V board. The Milk-V Pioneer’s RISC-V cores are pretty underpowered (though still better than the Milk-V Mars), but the point is that it works, and it opens the door to more games in the future. Original development (when the developer first got Stardew Valley working) began on the StarFive VisionFive2.

As for Stray, it’s running on the same machine that the developer got The Witcher 3 running on. It also runs slowly, but as an Unreal Engine 4 game, it’s massive progress to get it working. If Stray becomes completely playable, it’s likely that it would also improve performance of other Unreal Engine games, too.

How The Witcher 3 runs on RISC-V

It’s very, very complex

In order to run applications compiled for the x86_64 architecture, Box64 uses Dynarec, a shorthand term for dynamic recompilation. x86_64 is a CISC (Complex Instruction Set Computer) architecture, which offers a large set of complex instructions capable of performing tasks like memory operations and arithmetic in a single instruction. On the other hand, RISC-V follows the RISC (Reduced Instruction Set Computer) philosophy, featuring a simpler, more streamlined set of instructions. This difference means that x86_64 code, with its complex instructions, must be translated into sequences of simpler RISC-V instructions.

This process of converting x86_64 code into RISC-V instructions is handled by Dynarec Box64. In this system, ptitSeb explains, blocks of x86_64 instructions are translated into equivalent RISC-V instructions during runtime. These blocks, called “dynablocks,” are then stored and reused when the same x86_64 code is encountered again, reducing the need for repeated translations and improving overall efficiency. As an example, if you have a sequence of x86_64 opcodes, a dynablock is an associated sequence of RISC-V opcodes that perform the same logic.

This translation comes with a number of problems. Inherently, x86_64 can perform complex operations in a single instruction, whereas RISC-V requires multiple simpler instructions to achieve the same result. For example, tasks like loading data from memory and performing calculations need to be split into multiple steps on RISC-V. Additionally, translating features like x86_64’s flags into RISC-V instructions requires extra effort, as RISC-V has no flags at all.

As it stands, RISC-V translation is still in its infancy, but the architecture as a whole is continuously moving forward. With more hardware coming out built on it and developers spending more time on it, it’s looking more and more likely that at some point, development will begin to snowball. It’s not going to be powering a gaming handheld or anything anytime soon, but it’s certainly improving.